In a traditional master/slave memory architecture, a processor accesses main system memory through a memory controller, which provides significant control oversight for each memory transaction. To schedule memory transactions the memory controller manages large amounts of information about the state of various components of the system like the address/command bus, data banks, and data bus, among others. During each memory read, the memory controller issues specific commands to the memory modules to micro-manage every aspect of the operation, such as row activation, column selection, bit line precharge, and the like. This puts pressure on the address/command bus in terms of performance. The memory controller also keeps track of large amounts of state for potentially hundreds of independent memory banks to provide conflict-free accesses. At appropriate times, the memory controller may also issue maintenance commands, such as DRAM refresh, for example. In heterogeneous memory systems, the memory controller may perform different maintenance requirements for different memory modules. Further, the memory controller performs arbitration between memory modules for date transfers on the shared memory bus.
It is clear that managing large memory systems is extremely complex, and requires maintaining large amounts of state, and careful coordination to complete a single transaction. This significantly increases the complexity of the memory controller. Thus, the current master-slave interface between the memory controller and memory modules with completely centralized control is not scalable and not well suited to accommodate the increasing capacities and larger bandwidth requirements desirable for future computer systems.